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Altera_Forum's avatar
Altera_Forum
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17 years ago

Clock Noise?

Hello,

I am using a cyclone II fpga and have a 25 MHz clock going into a dedicated clock pin. I have a simple DFF to divide the clock by half to 12.5 MHz and i am looking at that output with a frequency meter.

There is a also a PC 104 on the board. When the PC-104 is not on the board the clock divide is proper. After the PC-104 boots up the 12.5 Mhz output gets noisy.

The Pc104 is some how affecting the 25 MHZ clock inside the FPGA.

Has anyone seen this before?

I cant find a Schmitt Trigger input in cylocne II.

Thanks for any help.

~Matt

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hi Matt,

    Do you mean noisy in amplitude or frequency? i.e. is it Jitter?

    What does the input clock like in both situations? Have you viewed the in and out clocks with an Oscilloscope?

    It sounds to me like a signal integrity issue. Do you run the clocks tracks near the PC104 on your PCB?

    Have you followed all the guidelines for PSU decoupling etc on your PCB?

    Sorry for all the questions, but hopefully it will give you some pointers of things to look out for.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Yes, the problem is most likely caused by SSO (simultaneous switching outputs) noise. It's particularly critical with large lead frame PQFP packages. Also insufficient power supply decoupling and ground trace inductance can bring it on.

    There are only limited means to fight it in an existing design. Reduction of output drive strength is the most effective, also utilisation of differential I/O standards for clock inputs. In addition, you should care for a fast rising clock input signal without overshoots.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Thank You for your quick reply's and ideas.

    After further investigation i discovered the same 25Mhz clock signal was driving an Ethernet chip. That Ethernet chip was probably causing a "ring" on the clock signal. And i could not see this on an oscilloscope.

    I was able to cut the trace going to the chip and use an additional FPGA output to drive the Ethernet clock.

    This cleaned up my issues.

    I probably need to review Altera's design guidelines before my next project.

    Thanks again.

    ~Matt