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Altera_Forum
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17 years ago

Clock Noise?

Hello, I am using a cyclone II fpga and have a 25 MHz clock going into a dedicated clock pin. I have a simple DFF to divide the clock by half to 12.5 MHz and i am looking at that output with a ...
Altera_Forum's avatar
Altera_Forum
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17 years ago

Thank You for your quick reply's and ideas.

After further investigation i discovered the same 25Mhz clock signal was driving an Ethernet chip. That Ethernet chip was probably causing a "ring" on the clock signal. And i could not see this on an oscilloscope.

I was able to cut the trace going to the chip and use an additional FPGA output to drive the Ethernet clock.

This cleaned up my issues.

I probably need to review Altera's design guidelines before my next project.

Thanks again.

~Matt