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Altera_Forum
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17 years ago

Clock Noise?

Hello, I am using a cyclone II fpga and have a 25 MHz clock going into a dedicated clock pin. I have a simple DFF to divide the clock by half to 12.5 MHz and i am looking at that output with a ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Yes, the problem is most likely caused by SSO (simultaneous switching outputs) noise. It's particularly critical with large lead frame PQFP packages. Also insufficient power supply decoupling and ground trace inductance can bring it on.

There are only limited means to fight it in an existing design. Reduction of output drive strength is the most effective, also utilisation of differential I/O standards for clock inputs. In addition, you should care for a fast rising clock input signal without overshoots.