clock newtork delay and intradomain skew

I'm still a little confused. If a PLL in the FPGA is generating both of these clocks, your .sdc should look something like this:

# internal clock that drives the output register

create_generated_clock -name output_clk -source <PLL_input_clock_pin> <relation_to_source> <PLL_output_clock_pin_1>

# output clock to drive downstream device

create_generated_clock -name emif_clk_int -source <PLL_input_clock_pin> <relation_to_source> -phase 90 <PLL_output_clock_pin_2>

# extra generated clock to define clock coming out of FPGA going to downstream device

create_generated_clock -name emif_clk -source <PLL_output_clock_pin_2> -multiply_by 1 <FPGA_clock_output_port>

# false path so data analysis is not performed on output clock

set_false_path -to <FPGA_clock_output_port>

# output delays; you need to have separate max and min delays

set_output_delay -max -clock emif_clk 4.5 [get_ports LC0]

set_output_delay -min -clock emif_clk <min_value> [get_ports LC0]

set_output_delay -max -clock emif_clk 4.5 [get_ports LC1]

set_output_delay -min -clock emif_clk <min_value> [get_ports LC1]

set_output_delay -max -clock emif_clk 4.5 [get_ports LC2]

set_output_delay -min -clock emif_clk <min_value> [get_ports LC2]

# multicycle so correct latch edge is used

set_multicycle_path -from output_clk -to emif_clk -end -setup 2

Let me know if this matches your design, which is still unclear.