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Altera_Forum's avatar
Altera_Forum
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8 years ago

clock newtork delay and intradomain skew

Hi, I have a flip flop in my fpga which is driving output pins (reg to output path). The clock of this is 5ns and the one outside fpga is 5ns (phase shifted by 90). The phase shifted clock is g...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

I'm a little confused about the clock to the "downstream" device. Are you saying it is generated by an FPGA PLL that is introducing a 90 degree phase shift from the one used for the output register (so the latch clock is 1 cycle plus 90 degrees (1.25 ns) later? Sounds like you might need multicycle. Can you post the waveform view report of the failing path and your .sdc?