clock mux, clock dividers and best clock constraints to use

1) Looks good, but shouldn't there by a -name? Also, it seems like by 1 of DTC_CTSROOT would be the 10MHz clock and have a divide by 2, while bit 2 would be a divide by 1. I don't know what logic you have to divide down, but am just assuming it's a counter.

2) This is wrong. There can't be a register between the -source and the target. You want your lines in 1) and then add:

create_generated_clock -name clk5M -source [get_pins {clk_divider|DTC_CTSROOT_1|Q|q}] [get_pins {clk_mux_2to1|Z|combout}]

create_generated_clock -name clk10M -source [get_pins {clk_divider|DTC_CTSROOT_2|Q|q}] [get_pins {clk_mux_2to1|Z|combout}] -add

set_clock_groups -exclusive -group {clk5M} -group {clk10M}

The last one cuts timing between these clocks, ensuring no paths are analyzed where clk5M drives the launch register and clk10M drives the latch, or vice-versa.

get_keepers only does enpoints of a timing path, i.e. FFs, IO ports, RAMs, DSPs. Your use of get_pins works just as well and is necessary for the combinatorial mux output. There are multiple get_* commands that overlap in one way or another and when it makes sense, either one will work. get_pins is the one used by ASIC tools, but users often find it annoying(which is why it has things like -compatibility_mode, to make it work more like a simple wildcard to the name. The -hierarchical matching is confusing to most.

Just to be safe, put a keep on your mux:

(* keep *) wire Z;

Quartus synthesis should preserve this anyway, but I've gotten in the habit of doing that.