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arife's avatar
arife
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3 years ago

clock jitter simulation of LVDS IP

Hi, I am using LVDS RX IP with 1.6 Gbps data rate with 800MHz inclock frequency. I would like to check jitter performance in simulation. I have created a a testbench that applies jitter 5ps constan...
skbeh's avatar
skbeh
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3 years ago

As I understand, when using LVDS RX SERDES IP with RX non-DPA mode, inclock source must be source from dedicated clock pin, cannot source from non-dedicated IO PLL output clock.


Suspect that the PLL is not able to detect the clock correctly which cause the PLL not able to locked at 800Mhz.

The suggestion is to try first with lower inclock (i.e. 200Mhz) to see if the PLL can lock.