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Zak's avatar
Zak
Icon for New Contributor rankNew Contributor
6 years ago

Clock Input voltage can be higher than VCCIO on Cyclone V devices?

Hello everyone, I need to connect one 1.8V CMOS clock generator to a clock input pin of the IO bank I use for DDR3L (1.35V). Since VCCPD=2.5V and VCCIO=1.35V on that bank, I'm not sure I can connec...
YuanLi_S_Intel's avatar
YuanLi_S_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi Andrea,

I am assuming you are using differential SSTL-135 for DDR3L. The VCCIO used for this I/O Standard is 1.35V and VCCIO used for 1.8V LVCMOS is 1.8V. Thus it cannot be placed in the same bank. It would be better if you could place I/O standard of 1.8V on bank with VCCIO of 1.8V for stable signal integrity.

Thank You.