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Honored Contributor
Honored Contributorclock generation from cyclone3
hi,
i want to generate 216Hz clock from cyclone3 pll mega function with 8.192MHz as pll input , but pll is not supporting. if i generated using logic elements is there any problem (with suitable i/p clock)? is it possible to access all the 5 outputs of pll? i hope u can help thanks5 Replies
Altera_ForumIs this question somehow related to the original post?
In any case, you can use a counter for that.- Altera_Forum
hi..please tell how to write
vhdl code for frequency divider with 50% duty cycle. regards - Altera_Forum
Use the output clock signal of one PLL as input to the second PLL.
Lokla - Altera_Forum
hi,
please tell how to cascade plls in cyclone3 regards krishnam raju - Altera_Forum
I dont think you can get a 216MHz clock out of a 8.192 MHz input at all. At least not exactly. If you want to get close to it, you can try to cascade 2 PLLs, but not sure about JItter and clock quality.
Lokla
