Honored Contributorhi,
i want to generate 216Hz clock from cyclone3 pll mega function with 8.192MHz as pll input , but pll is not supporting. if i generated using logic elements is there any problem (with suitable i/p clock)? is it possible to access all the 5 outputs of pll? i hope u can help thanks
Honored ContributorI dont think you can get a 216MHz clock out of a 8.192 MHz input at all. At least not exactly. If you want to get close to it, you can try to cascade 2 PLLs, but not sure about JItter and clock quality.
LoklaHonored Contributorhi,
please tell how to cascade plls in cyclone3 regards krishnam rajuHonored ContributorUse the output clock signal of one PLL as input to the second PLL.
LoklaHonored Contributorhi..please tell how to write
vhdl code for frequency divider with 50% duty cycle. regardsHonored ContributorIs this question somehow related to the original post?
In any case, you can use a counter for that.
