Altera_ForumHonored Contributor17 years agoclock generation from cyclone3 hi, i want to generate 216Hz clock from cyclone3 pll mega function with 8.192MHz as pll input , but pll is not supporting. if i generated using logic elements is there any problem (with suitabl...Show More
Altera_ForumHonored Contributor17 years agohi..please tell how to write vhdl code for frequency divider with 50% duty cycle. regards
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