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Altera_Forum
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15 years ago

"clock enable" or tickle designing (VHDL)

Hi,

Could you tell us some good practice, recommandations to design with a "clock enable" signal ?

In order to work with low frequency signals (<10 kHz), I would like to design with a tickle (frequency approx. 100 kHz). It will reduce counters size, power consumption... 

PROCESS (CLK, RST_n)
   BEGIN – PROCESS
      IF RST_n = '0' THEN
         Outsignal <= '0';
      ELSIF CLK'event AND CLK = '1' THEN
         IF (CE = '1') THEN -- clock enable
            Outsignal <= '1';
         END IF;
     END IF;
END PROCESS;

"clock enable" must be one clock width

no logic outside clock enable statement in process ?

What are other good coding/desiging "rules" ?

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    The process you have written will generate only a enable flipflop. Please be specific and more clear about your problem so that people can give you suggestions.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Dear mm,

    that is the correct template to generate logic with active low asynchronous reset and a clock enable.

    You are correct in that the CE signal must just one clock wide and that all logic (except for reset) must be described within the IF CE = "1" THEN ... END IF; block.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Thanks for answer.

    I think :

    clock enable signal must be global through the entire design : from top level entity (in which Clock Enable signal is generated) to the lowest level (counters, registers .... )

    I think it is a good point.

    BUT, you have to pay attention about external signals which can escape the tickle (alias Clock Enable). I mean : if signals are changing outside of the ClockEnable, they will not be "captured". It is information only.

    My goal is to reduce number of Logicl Elements needed because one part of my design work on low frequency signals.

    I have counters to measure Period of some signals. clocking them at 50MHz will consume many logical elements (because of place) and power (because of switching).

    @ rsenthil78 : No problem here, I wonder if you know good practice to design with clockenable signal.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    In general, the tools will automatically promote the CE signal to be a global signal. It's worth to check if is, but you shouldn't have to do anything.

    "BUT, you have to pay attention about external signals which can escape the tickle (alias Clock Enable). I mean : if signals are changing outside of the ClockEnable, they will not be "captured". It is information only."

    Well, of course. This is a generic concern.

    A flip-flop only captures it's input at the clock edge. Any changes at the input between the clock edges are ignored -- this is the basic operation of a flip-flop.

    Likewise, a flip-flop with a clock enable only captures it's input at the clock's edge and only when the clock is enabled

    Oh yeah, there's one more important thing: timing constraints.

    You need to specify multi-cycle constraints or, otherwise, Quartus will not now about clock enabled and will (try) to produce a design that operates at the clock's frequency.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    [information only]

    In my example, "Outsignal" = '1' during at least one period of CE signal, of course.