Forum Discussion
EugenyB
Occasional Contributor
Occasional ContributorClock enable for connected module not having it
Consider the following code:
reg [1:0] div = {2{1'b0}};
always@(posedge clock)
div[1:0] <= div[1:0] + 1'b1;
wire clk_enable = (div[1:0] == 2'b00);
always@(posedge clock or nege...
EugenyBOccasional Contributor
Occasional ContributorI decided to go the other route changing the architecture rather than considering more and more complex clocking problem. Now I use one control signal using synchronizer, and ensure that data is held several cycles after synchronizer finishes to ensure set up and hold times are not violated when circuit driving remote update latches the data.
Thanks for your help.
