Forum Discussion
EugenyB
Occasional Contributor
Occasional ContributorClock enable for connected module not having it
Consider the following code:
reg [1:0] div = {2{1'b0}};
always@(posedge clock)
div[1:0] <= div[1:0] + 1'b1;
wire clk_enable = (div[1:0] == 2'b00);
always@(posedge clock or nege...
sstrell
Super Contributor
Super ContributorSo use a clock control block or a separate PLL. You might also need multicycle timing exceptions in your .sdc file to line up the setup and hold timing correctly.
EugenyBOccasional Contributor
Occasional ContributorThank you very much! I have several questions left:
1. how many clock controllers can be set up in Cyclone 3? They seem using dedicated logic, but I can not find this information in the documentation;
2. should I pass both master clock, and slower clock through clock controllers for compensate for the delays in them? (see below)
