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Altera_Forum
Honored Contributor
Honored ContributorClock doubler without PLL
I have a design where I need to double an incoming frequency but lo and behold I made a mistake of not putting this input signal in a dedicated clock input pad.... so, it would appear that PLL:...
Altera_ForumHonored Contributor
Honored ContributorFor a proper fpga based design, I am afraid the notion of doubling clock without pll will get you in a timing mess.
Consider using the slow clock but use two processing channels (odd/even samples). Though a pain but should be equivalent. The problem would be at final crossover to double rate... This is equivalent to having a DDR approach inside fpga.
