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Altera_Forum's avatar
Altera_Forum
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15 years ago

Clock divider

I need to have a continuous clock input to my traffic light assignment. A clock divider from 100MHz to 1Hz is needed. But I dont know how to write the code as I am new to vhdl. Anyone can help? :confused: or is there any other way I can get a continuous clock input so that I can program the code directly to the board.. ? Then the green light represented by green led wil light up for 30s, yellow for 2s..

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    You can use the Altera Megawizard to generate this logic for your device.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Sounds like you need to have a large counter (25 bits or so) and "and" all the bits together to form an enable for other registers to give you a 1Hz clock rate.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    how to use the altera megawizard..

    --- Quote End ---

    Hi,

    use a counter and an edge detection in order to generate an enable signal for your register. E.g

    module ena_gen (clk,ena_out);

    input clk;

    output ena_out;

    reg [26:0] count;

    reg edge_det;

    always @(posedge clk) begin

    count <= count + 1;

    edge_det <= count[26];

    end

    assign ena_out = !edge_det & count[26];

    endmodule

    Kind regards

    GPK
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    This is Verilog - he asked for VHDL

    --- Quote End ---

    Hi Tricky,

    you are right, I should read all posts, but maybe he has now a starting point ...

    Kind regards

    GPK
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    Hi Tricky,

    you are right, I should read all posts, but maybe he has now a starting point ...

    Kind regards

    GPK

    --- Quote End ---

    Hi,

    now the VHDL version. Maybe not the best way for VHDL, but I'm not a VHDL expert.

    LIBRARY ieee;

    USE ieee.std_logic_1164.ALL;

    USE ieee.std_logic_unsigned.ALL;

    ENTITY ena_gen IS

    PORT

    (

    -- Input Ports

    clk: IN std_logic;

    -- Output Ports

    ena_out : OUT std_logic );

    END ena_gen;

    ARCHITECTURE RTL OF ena_gen IS

    SIGNAL count : std_logic_vector ( 26 DOWNTO 0);

    SIGNAL edge_det: std_logic;

    BEGIN

    -- Pulse counter

    counter : PROCESS (clk)

    BEGIN

    IF rising_edge (clk) THEN

    count <= count + '1';

    edge_det <= count(26);

    END IF;

    END PROCESS counter;

    ena_out <= (NOT edge_det) AND count(26);

    END rtl;

    Kind regards

    GPK