Clock divider

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Hi Tricky,

you are right, I should read all posts, but maybe he has now a starting point ...

Kind regards

GPK

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Hi,

now the VHDL version. Maybe not the best way for VHDL, but I'm not a VHDL expert.

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.ALL;

ENTITY ena_gen IS

PORT

(

-- Input Ports

clk: IN std_logic;

-- Output Ports

ena_out : OUT std_logic );

END ena_gen;

ARCHITECTURE RTL OF ena_gen IS

SIGNAL count : std_logic_vector ( 26 DOWNTO 0);

SIGNAL edge_det: std_logic;

BEGIN

-- Pulse counter

counter : PROCESS (clk)

BEGIN

IF rising_edge (clk) THEN

count <= count + '1';

edge_det <= count(26);

END IF;

END PROCESS counter;

ena_out <= (NOT edge_det) AND count(26);

END rtl;

Kind regards

GPK