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Altera_Forum's avatar
Altera_Forum
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16 years ago

Clock divider

I need to have a continuous clock input to my traffic light assignment. A clock divider from 100MHz to 1Hz is needed. But I dont know how to write the code as I am new to vhdl. Anyone can help? :conf...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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how to use the altera megawizard..

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Hi,

use a counter and an edge detection in order to generate an enable signal for your register. E.g

module ena_gen (clk,ena_out);

input clk;

output ena_out;

reg [26:0] count;

reg edge_det;

always @(posedge clk) begin

count <= count + 1;

edge_det <= count[26];

end

assign ena_out = !edge_det & count[26];

endmodule

Kind regards

GPK