Clock Divider and PLL Best Practices

Hi Alex

You just need to ensure you comply to I2C protocol when you creating SCL and SDA line.

The purpose of using PLL is to provide synchronization between external clock and internal clocks. When a PLL locks onto the input frequency, there is a limited variation of that signal at the output. This is good for jitter reduction and clock skew control of the design. It is depends on your design whether you need a PLL.

If the input reference clock of PLL is of the same frequency as its output clock, then it is the same domain.

There are some sample I2C design available in open source. You can make use of that as your design reference.

Thanks.

Eng Wei