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Alex77's avatar
Alex77
Icon for New Contributor rankNew Contributor
5 years ago

Clock Divider and PLL Best Practices

Hi Everybody,

I am new to FPGA programming and have some questions regarding the clocks in FPGA. I started to learn Verilog and as part of the first project design, I need to use I2C to communicate to an external device. Since I am new to FPGA I decided not to use existing I2C cores, but write my own (just for learning purpose). In my case, it is simplified one master to one slave communication, so I2C looks simple enough to implement.

I actually have a working design, but now I have a few questions about clock signals. My clock is running at 50MHz. For I2C I need SCL clock to run at 400kHZ/100kHZ. I created a clock divider with a counter. However, I saw that this type of clock divider in FPGA is frowned upon.

So, here is my first question - is this "clock" for SCL considered a clock? I don't use it to drive always @ (posedge ) blocks (it is run by system 50MHz **bleep**). I use this "clock" to generate the SCL signal and use it inside always block to know when to change the SDA signal.

The next question is about PLL. I can use PLL to generate a 400kHz clock. But it looks like to be able to work with the rest of the logic which is driven by 50MHz clock I either need to use 50Mhz clock inside I2C logic and use PLL just to drive SCL, or drive I2C logic with 400kHz clock. The latter will require extra synchronization between 50MHz logic and 400kHz logic. In fact, it is not 400kHz but at least 800kHz since the SDA signal can change only in the middle of positive or negative SCL cycle. It looks like an overcomplicated design, but if it will make system more stable it is worth it. So my question is - does it make sense to use PLL for this purpose?

And one more PLL related question. Is the clock generated by PLL a different clock domain with regards to the clock that drives PLL?

Thanks,

Alex.

3 Replies

  • ak6dn's avatar
    ak6dn
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Since it appears you are generating a 'master' (not 'slave') I2C device, the clock signal you are generating is not a clock for your internal logic, but just an output signal, to be used by the external device. So Quartus does not think of it as a clock.

    As to how you run your logic at an effective rate of 400kHz/100kHz the way I have done this is to build a master I2C state machine that runs on the internal 50MHz clock, but only changes state at the desired rate (say 400kHz). I will do this with a counter running on 50MHz that generates a one clock wide 'enable' pulse every 400kHz. A simple 9b counter can handle division down to 97kHz.

    Using the PLL to generate a synchronized 400kHz/100kHz clock is certainly possible, but is getting way more complicated than need be IMHO.

  • EngWei_O_Intel's avatar
    EngWei_O_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    5 years ago

    Hi Alex

    You just need to ensure you comply to I2C protocol when you creating SCL and SDA line.

    The purpose of using PLL is to provide synchronization between external clock and internal clocks. When a PLL locks onto the input frequency, there is a limited variation of that signal at the output. This is good for jitter reduction and clock skew control of the design. It is depends on your design whether you need a PLL.

    If the input reference clock of PLL is of the same frequency as its output clock, then it is the same domain.

    There are some sample I2C design available in open source. You can make use of that as your design reference.

    Thanks.

    Eng Wei

    • EngWei_O_Intel's avatar
      EngWei_O_Intel
      Icon for Frequent Contributor rankFrequent Contributor
      5 years ago

      Hi Alex

      I will transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

      Eng Wei