Clock Divider and PLL Best Practices

Since it appears you are generating a 'master' (not 'slave') I2C device, the clock signal you are generating is not a clock for your internal logic, but just an output signal, to be used by the external device. So Quartus does not think of it as a clock.

As to how you run your logic at an effective rate of 400kHz/100kHz the way I have done this is to build a master I2C state machine that runs on the internal 50MHz clock, but only changes state at the desired rate (say 400kHz). I will do this with a counter running on 50MHz that generates a one clock wide 'enable' pulse every 400kHz. A simple 9b counter can handle division down to 97kHz.

Using the PLL to generate a synchronized 400kHz/100kHz clock is certainly possible, but is getting way more complicated than need be IMHO.