Altera_Forum
Honored Contributor
11 years agoClock Crossing and FIFOs
Hello all,
I am having a custom design in handwritten VHDL and a design implemented in DSP Builder and they interface using some 16bit signals BUT running on different clocks. I was wondering what kind of synchronization I should use for this interface. I suspect I should use the dual clock FIFO IP but I am not sure if this is the suggested way. Also if the difference in the clocks is 100MHz and 150MHz and the sample ratio of the DSP Builder module is in the rate of kHz then how deep should the FIFO be? I am not expecting any overflow and I do not need any real FIFO functionality just the snychronization of the two clock domains for a bulk of data signals. Regards