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Altera_Forum
Honored Contributor
11 years agoClock Crossing and FIFOs
Hello all, I am having a custom design in handwritten VHDL and a design implemented in DSP Builder and they interface using some 16bit signals BUT running on different clocks. I was wonder...
Altera_Forum
Honored Contributor
11 years agoIn general a FIFO is a good way to go. You'll have to figure out how deep it needs to be.
If only one transaction ever happens at a time you don't need a FIFO. When the data source has data to transfer it asserts a flag (call it data_ready). The data sink will synchronize that signal and monitor the synchronized version (call it data_ready_sync). When the data sink sees data_ready_sync go high it latches the data then asserts a flag back to the data source (call it data_ready_ack). The data source synchronizes this signal and monitors the synchronized version (call is data_ready_ack_sync). When the data source sees data_ready_ack_sync go high it knows the data sink has latched the data and it can now deassert data_ready. Then when the data sink sees data_ready_sync go low it can deassert data_ready_ack and the transaction is complete. Sounds a little convoluted when written out like this but drawn on paper it's very simple. This only works if each transaction always completes before a new data word is ready. Otherwise a FIFO is the way to go.