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Altera_Forum
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11 years ago

Clock Crossing and FIFOs

Hello all, I am having a custom design in handwritten VHDL and a design implemented in DSP Builder and they interface using some 16bit signals BUT running on different clocks. I was wonder...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Actually I just need to transfer a bundle of data between the clock domains one at a time. So I think you are right. The procedure you describe is the way to go and thank you so much for it!!