Forum Discussion

verna's avatar
verna
Icon for New Contributor rankNew Contributor
3 years ago

clock control signal problem on Cyclone V GT

I'm working with the Cyclone V GT development board.My design only needs to use frequency divider to get the signal, I tried to use 240MHz to divide the frequency and can get the signal successfully,...
verna's avatar
verna
Icon for New Contributor rankNew Contributor
3 years ago

Hi SyafieqS,

I still not solve this problem. There's not error suggest. The clock control block warning suggest is Warning (15846): ena port of Clock Buffer Block "ALTCLK_altclkctrl_9kh:ALTCLK_altclkctrl_9kh_component|sd1" is connected to GND.