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verna's avatar
verna
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3 years ago

clock control signal problem on Cyclone V GT

I'm working with the Cyclone V GT development board.My design only needs to use frequency divider to get the signal, I tried to use 240MHz to divide the frequency and can get the signal successfully,...
verna's avatar
verna
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3 years ago

Hi, SyafieqS

I tried the following method but it didn't work.

I try to use Clock Control Block (ALTCLKCTRL) to wire my input port and output port wire my counter to divide use three port pin outputs, my output ports one of which is SMA_CLKOUT on cyclone v gt and the other two pin outputs of Terasic XTS-HSMC, so I use REFCLK_QL3_P of HSMC port B connected to the clock input pin.