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verna's avatar
verna
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4 years ago

clock control signal problem on Cyclone V GT

I'm working with the Cyclone V GT development board.My design only needs to use frequency divider to get the signal, I tried to use 240MHz to divide the frequency and can get the signal successfully,...
SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
4 years ago

Hi Chuang,


May I know if there is any update?


  • verna's avatar
    verna
    Icon for New Contributor rankNew Contributor
    4 years ago

    Hi SyafieqS,

    Sorry,I still don't understand how to use it.

    My project use Cyclone V GT REFCLK_QL3_P (X4) to input clock, because I use three ports to output one is on Cyclone V GT SMA_CLKOUT and the other use Terasic XTS-HSMC (HSMB_CLK_OUT_P2 and HSMB_CLK_OUT_N2).