Hi Lambert,
I had further confirmed with my team that since you're using async input and async output (neighter system_sync nor source sync design) so not need to set input delay and output delay, just timing exceptions will do.
And because fr_clk and hr_clk comes from the same PLL output, I think "derive_pll_clock" constrain will be okay
Yes, the derive_pll_clocks constraint will take care of the clock relationships from the PLL
(1) Just because there's hr_ddio and fr_ddio, I need follow "Opposite-Edge Capture Edge-Aligned Output" to set the DDR constrians for each *_ddio part or only set the DDR constrians for only fr_ddio?
I think your mentioned situation suits well to "Opposite-Edge Capture Edge-Aligned Output" if check this document illustration https://cdrdv2-public.intel.com/653688/an433.pdf. For "Opposite-Edge Capture Edge-Aligned Output", do not use any multicycle or delay exceptions for opposite-edge transfers. The only exceptions necessary for correct timing analysis are false path exceptions.
So, set false path DDR constraints to only fr_ddio will do like example show in this link https://www.intel.com/content/www/us/en/docs/programmable/683780/22-1/full-rate-or-half-rate-ddio-output-register.html
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