Hi, all fpga : 10ax115N3f45I1sg quartus : 18.0.0 standard version Now I'm using GPIO IP core to design using bus lvds. And for this IP, I use half rate design, read and wirte use seperate cl...
Probably should be fine since there's no timing violation.
Since that's asynchronous input and output so not need to set input delay and set output delay. Without set input delay and set output delay, you wouldn't see any timing violation one.
For input, I only used it as async input (neighter system_sync nor source sync design), so for the timing path, I need care fr_clk -> hr_clk (clock domain crossing), and hr_clk domian(for the registers in the core, it uses the hr_clk continue to process the data). And because fr_clk and hr_clk comes from the same PLL output, I think "derive_pll_clock" constrain will be okay.
///// for output
For output, I only used it as async output (neighter system_sync nor source sync design).
For input din[3:0] (data from hr_clk domain), and there's hr_clk -> hr_clk, hr_clk-> fr_clk, fr_clk->port(just because async design, there's no clock output), so tool will need only analysis hr_clk-> hr_clk, and hr_clk->fr_clk.
(1) Just because there's hr_ddio and fr_ddio, I need follow "Opposite-Edge Capture Edge-Aligned Output" to set the DDR constrians for each *_ddio part or only set the DDR constrians for only fr_ddio?
(2) And because I used the output as async output without clock output, I will not set the output delay and only need to set the exception constrain?
Reason for "Opposite-Edge Capture Edge-Aligned output":
As in the picture, din input is aligned to the rising edge ck_hr, and hr_ddio will capture the din[0] at the falling edge and capture the din[2] at the next rising edge. dout will be delayed one-cycle of ck_hr (as the red rectangular), right?
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