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Altera_Forum's avatar
Altera_Forum
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18 years ago

Clock Assignment

I am very new to this field.

I have some questions and it would be very helpful if u can answer some of them.

I need to assign global and regional lines to route my LVDS clock (INT_CLK) from CLK0 to FPLL1, from CLK0 to EPLL5 and 6; and from FPLL1 output to an external PLL. I am using tcl for this.

I wrote the follwoing command in my assignment editor:

set_instance_assignment GLOBAL_SIGNAL "GLOBAL CLOCK' -to "INT_CLK_P"

I have also tried using,

set_instance_assignment GLOBAL_SIGNAL -from "INT_CLK_P" -to "FPLL1"

set_instance_assignment GLOBAL_SIGNAL -from "INT_CLK_P" -to "EPLL5"

No matter what I do I am not able to assign the desired global and regioanl signals.

My report just says that a global line has been allocated to INT_CLK, but it does not tell me whether it goes to FPLL1 or EPLL5 or 6.

The very first question is that do I even need a global line to connect CLK0 to FPLL1 as there is a dedicated line for them.

Secondly, to route to FPLL1 or any PLL, do I use "FPLL1" or "EPLL5" etc in the syntax or there is some other way to define them.

Please let me know.

Regards,

TM

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    --- Quote Start ---

    The very first question is that do I even need a global line to connect CLK0 to FPLL1 as there is a dedicated line for them. Secondly, to route to FPLL1 or any PLL, do I use "FPLL1" or "EPLL5" etc in the syntax or there is some other way to define them.

    --- Quote End ---

    If you use the right combination of dedicated clock input pin and PLL (or combination of PLL and dedicated clock output pin for a clock you are driving out), you will get the "dedicated line" automatically. I have had a case where using an unnecessary global signal assignment resulted in a global buffer being used needlessly instead of the intended dedicated line.

    Check the device handbook (if you haven't already) to make sure it is even possible to route from the dedicated clock input pin you want to use to both the fast and enhanced PLLs. Depending on the device and the combination of pins and PLLs, this might be a case where you can use a "dedicated line" for one of the PLLs but have to go through a global buffer for the other PLL.

    I have not tried designating the PLLs in the global signal settings the way you did it. I didn't check into it, but I think it is incorrect. If it is correct in the first place to do a point-to-point (as opposed to single-point) global signal assignment to the PLL, you probably need the PLL node name.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    Thanks a lot Brad.

    I specified the node names and it's working now :)