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The very first question is that do I even need a global line to connect CLK0 to FPLL1 as there is a dedicated line for them. Secondly, to route to FPLL1 or any PLL, do I use "FPLL1" or "EPLL5" etc in the syntax or there is some other way to define them.
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If you use the right combination of dedicated clock input pin and PLL (or combination of PLL and dedicated clock output pin for a clock you are driving out), you will get the "dedicated line" automatically. I have had a case where using an unnecessary global signal assignment resulted in a global buffer being used needlessly instead of the intended dedicated line.
Check the device handbook (if you haven't already) to make sure it is even possible to route from the dedicated clock input pin you want to use to both the fast and enhanced PLLs. Depending on the device and the combination of pins and PLLs, this might be a case where you can use a "dedicated line" for one of the PLLs but have to go through a global buffer for the other PLL.
I have not tried designating the PLLs in the global signal settings the way you did it. I didn't check into it, but I think it is incorrect. If it is correct in the first place to do a point-to-point (as opposed to single-point) global signal assignment to the PLL, you probably need the PLL node name.
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