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Altera_Forum
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15 years ago

clkn input clock can not drive PLL on stratixII

I'm working on StratixII device, and in would like to inject a clock on the CLK9n input pin of my FPGA to drive a PLL. When looking at the Stratix II Device Handbook, it is possible to do that by ...
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Altera_Forum
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15 years ago

I don't see anything in the user's guide that indicates the CLKn pins can drive the PLL inclk pins. In fact it looks to me like it has to be CLKp pin.

The only exception I can see is that some of the CLKn pins can drive the global clock network. But only the ones on the Top and Bottom of the devices. CLK9n is not one of these (see table 1-22) http://www.altera.com/literature/hb/stx2/stx2_sii52001.pdf

If you were using a CLKn pin listed in table 1-22 you could drive a global clock from that pin and then take the global clock as input to a PLL. It doesn't look like that's going to happen with CLK9n.

Jake