CLKCNTRL block placement conflicting with PLL placement

I am muxing two clocks generated from the same pll using the altclkctrl block. The connections look like below -

1'b0 ---> ALTCLKCTRL.inclk[0]

1'b0 ---> ALTCLKCTRL.inclk[1]

PLL_T1 - CLK[4] ---> ALTCLKCTRL.inclk[2]

PLL_T1 - CLK[5] ---> ALTCLKCTRL.inclk[3]

Internal Reg ---> ALTCLKCTRL.clksel[0]

1'b1 ---> ALTCLKCTRL.clksel[1]

But... I get following placement error in fitter... Any suggestions as to what may be happening?

TIA.

Sanjay

Info: CLKSELECT placement assigned the following 3 node(s) to these locations

Info: Node flir_top_wrapper:flir_top_wrapper_inst|flir_top:arch_normal.flir_top_inst|pxl_clk_mux:pxl_clk_mux_inst|pxl_clk_mux_altclkctrl_fne:pxl_clk_mux_altclkctrl_fne_component|sd2 is assigned to location CLKSEL_G0

Info: Node flir_top_wrapper:flir_top_wrapper_inst|flir_top:arch_normal.flir_top_inst|pxl_clk_mux:pxl_clk_mux_inst|pxl_clk_mux_altclkctrl_fne:pxl_clk_mux_altclkctrl_fne_component|sd1 is assigned to location CLKCTRL_G0

Info: Node clk_wrapper:clk_wrapper_inst|clk:arch_normal.clk_inst|clk_pll:clk_pll_inst|altpll:altpll_component|clk_pll_altpll:auto_generated|pll1 is assigned to location PLL_L2

Error: Cannot place Top/Bottom PLL "clk_wrapper:clk_wrapper_inst|clk:arch_normal.clk_inst|clk_pll:clk_pll_inst|altpll:altpll_component|clk_pll_altpll:auto_generated|pll1" in PLL location PLL_L2, because location does not accept Top/Bottom PLLs