Honored Contributor
Honored ContributorSee table 5, http://www.altera.com/literature/ds/ds_scg.pdf
DCLK max freq is stated at 20MHz. From page 10-9 of http://www.altera.com/literature/hb/cyc3/cyc3_ciii51010.pdf In Cyclone III devices, the active master clock frequency runs at a maximum of 40 MHz, and typically at 30 MHz. Cyclone III devices only work with serial configuration devices that support up to 40 MHz. Existing batches of EPCS4 manufactured on 0.15 µ process geometry support AS configuration in Cyclone III devices up to 40 MHz. However, batches of EPCS4 manufactured on 0.18 µ process geometry support only up to 20 MHz. EPCS16, EPCS64, and EPCS128 are not affected. My guess is that you have the EPCS4 manufactured on the 0.18u process, and it only supports 20MHz dclk. Some boards may configure because some of the EPCS4's can tolerate the 30MHz DCLK clock or the FPGA is below the typical 30MHz. Maybe try ordering a couple EPCS16's and solder them on the boards that are not configuring?
