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But if you're telling me that the FPGA latches the data of the previous cycle JUST before the FLASH sends out the next bit then there must be an FPGA spec for hold time on the data line--what is it and where can I get this information? I can't seem to find it in the data sheet.
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Basically yes. Actually, there is a general (not device specific) specification in Configuration Handbook:
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tH Data hold time after rising edge on DCLK 0 ns,
tSU Data set up time before rising edge on DCLK 5 ns
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The respective diagram is showing a falling DCLK edge, however.
Because of the simple fact, that EPCS data can't arive
before clock edge, this specification can be expected to be met generally. For the same reason, there is no particular delay matching requirement, the clock frequency is rather low anyway.
Using the same clock edge for source and destination is a common method with fast SPI interfaces to increase the timing margin. With AS configuration, the most likely signal quality issue is double clocking of EPCS device due to distorted DCLK to my opinion.
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