Honored Contributor
Honored ContributorMSEL is fine. I would imagine that the configuration sequence would not even start otherwise.
All of the configuration lines seem to be doing what is expected. The FPGA is sending out DCLK, CS, and ADI. The flash is also sending out DATA. It just won't configure unless I freeze the flash device. In fact I can turn on and off the problem by heating and cooling the FLASH device, not he FPGA. I believe it is a timing issue but I'm not sure what paramater isn't happy. I can't find any specs on the tsu/thold from the FPGA's perspective. The FLASH device calls out no more than a 15ns delay from the falling edge of DCLK to the rising edge of DATA. My FLASH is actually putting out data ~3-4nsec after the falling edge of DCLK. (just an aside)I don't necessarily agree with you on the FMAX. If your clock is running at 30MHz sending out data on the falling edge and another device is latching that data on the rising edge, then the data rate is 30MHz, not 15MHz. But if you're telling me that the FPGA latches the data of the previous cycle JUST before the FLASH sends out the next bit then there must be an FPGA spec for hold time on the data line--what is it and where can I get this information? I can't seem to find it in the data sheet (CH10). My DCLK and DATA trace lengths are almost matched, about 1mm difference. I am thinking about board assembly, too. This is a full-up RoHS compliant board. And I know the RoHS process is more stringent than a leaded: pre-heat boards, solder temperatures, etc. Have you ever seen problems like this caused by a poor assembly process? Thank you for the input.
