Honored Contributor
Honored Contributor1 - Check MSEL setting.
2 - Grab an oscilloscope and check the configuration lines are wiggling. 3 - Scope a working board and check the signal integrity of the configuration lines. It's possible your layout has a borderline timing issue (not likely). 4 - Sounds like these are first-run boards. My experience is that it's almost always the board house's fault when an issue like this occurs. 5 - Does the part configure via JTAG? --- Quote Start --- In my reading I noticed that the flash drives out on the falling edge of DCLK and the FPGA latches also on the falling edge--is this correct? It seems more logical for the FPGA to latch on the rising edge if the flash is sending out on the falling edge. Otherwise it would seem that the tsu would be rather tight. --- Quote End --- This scheme is correct because the clock is driven from the FPGA. The FPGA latches the data that is present on it's DATA input. Then the clock edge signal propagates along the board trace to the EPCS device where it then drives the next data bit out. Driving and latching on opposite edges would effectively reduce the fmax of the configuration scheme by 50% because the data signal would have half as much setup time before the latching edge. Jake
