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Hi, from what I see online, the 402Mhz speed is mentioned on some of the distributor's website, but Altera's website did not mention the FMax (core performance) for these chips. Which makes sense, since the Core FMax depends on various factors such as the complexity of routing, available resource, etc.
If you would like to know whether slower chips (such as speed grade 8) will work with your design, try selecting them in Quartus and compile your design again. If you do not encounter any timing error (assuming of course, that you have constrained them properly) then the chip should work.
So far, I've only run up to 100-120Mhz on these Cyclone IV E chips... (with Nios)
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Thanks for the reply. I have spoken to one of the guys at university and been told that in order to constrain my design I must start by defining all the external signal inputs to the FPGA. I'm working on this now, though I have to admit I'm not completely sure where to start.
I have data coming into the FPGA from an audio codec, and SPI line from a micro-controller. It is my understanding, that it is these signals that need to be constrained.
EDIT: For example, my SPI input from the micro-controller consists of three data lines; SCK, S_IN, SS, its just a simple slave peripheral. I have passed all these signals through flip-flop synchronizers, as I understand is required in order to synchronize to my system clock such that I can sample those signals on the rising edge of my system clock. If anyone could talk me though, or give advice on how to constrain these inputs it would be a HUGE help.
In fact, to begin with, I would appreciate it if someone could confirm that I have constrained my clocks correctly. In my design, I have an input pin 'CLOCK_50' which is tied to the 50Mhz clock of the De0-Nano, which is used as an input to a PLL megafunction which then outputs 'sys_clock', which is at 100Mhz. This is illustrated in the image below.
It is my understanding, that these are the only clocks that need to be constrained, since all inputs to the FPGA are synchronzed to and sampled on the rising edge of 'sys_clock'.
The code below is what I have used in my .SDC file to constrain these clocks, it is my understanding that this is sufficient.
#Base clock
create_clock -name {CLOCK_50} -period 20
# Clocks derivied from base clock
derive_pll_clocks
derive_clock_uncertainty
http://i68.tinypic.com/11aeurd.jpg Cheers, Chris.
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