Choosing Cyclone IV device/speed grade

So far I have learned that I must 'define' my clock signals using an .SDC file, which I have done successfully, using the following script;

# Base clock

create_clock -name {CLOCK_50} -period 20 [get_ports {CLOCK_50}]

# Clocks derivied from base clock

derive_pll_clocks

derive_clock_uncertainty

I no longer receive any error messages about my undefined clock signals.

Initially, after setting up my clocks in the .SDC file I received critical errors stating 'timing constraints not met'. But by reducing my system clock down from 200Mhz to 100Mhz (200Mhz was really not required). These critical errors have gone.

However, although the clocks are resolved (as far as I can see), I still have many unconstrained paths;

http://i64.tinypic.com/6p8137.jpg

I'm currently trying to gain a better understanding in order to understand resolve these issues. It's my hope that one of the tech guys at uni will be able to help.. though its no secret that they all dislike and lack experience with FPGA, for some reason.

EDIT: Ultimately, as the FPGA is only part of my project, I just need to get to the point where I can settle on a chip for my design as quick as possible. My design runs works on the De0-Nano, I just need to be sure I can move from to another device within the same family (Cyclone IV E), and be confident that moving from a speed grade 6 device to 7 or possibly 8 will not result in failure. I have researched and become familiar with EPCS (serial configuration IC), so I have a method to remotely configure the FPGA, but before I can begin investigating PCB layouts and circuit considerations I must, obviously, settle on a device.