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Honored Contributor
Honored ContributorChanging PLL settings without a new compilation
Hi, I am using Arria V GX FPGA and Quartus 13.1 and there are timing violations, so I need to try different PLL settings to try to fix them. Is there a way to change the PLL phase shift for examp...
Altera_ForumHonored Contributor
Honored ContributorHi Nial:
The problem, is you are dynamically changing the timing, so the static timing analyzer of Quartus will have way to determine timing for you. I have only used this for interface adjustments, (IE external high speed interfaces). And had a system with two clocks, a "Launch" clock and a "Latch Clock" across the interface that were skewed compared to each other. To determine the best setting, we found the failing boundary on both sides, and then picked a selection in the middle of the passing window. Internal timing should be left to the tool to work out and correct. If you are still failing timing, you should look at re-pipelining the design, or optimizing the layout. Pete
