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Altera_Forum's avatar
Altera_Forum
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12 years ago

Changing PLL settings without a new compilation

Hi, I am using Arria V GX FPGA and Quartus 13.1 and there are timing violations, so I need to try different PLL settings to try to fix them. Is there a way to change the PLL phase shift for examp...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Using dynamically configurable PLLs is a very powerful way to explore various configurations. So, it is well worth investing the time to get to grips with it. It becomes a very useful tool to fine tune interfaces, especially with external peripherals. If you can stomach instantiating a Nios to control it you will realise an enormous amount of flexibility.

However, I'm not sure I'd expect it to solve all your timing violations - assuming they're internal violations you're referring to. Shifting the phase of a clock is not going to benefit any block of logic that resided entirely on that clock domain. Are we discussing cross domain issues? Perhaps you can shed a little more light on the timing violations you have.

Regards,

Alex