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Altera_Forum
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12 years ago

Changing PLL settings without a new compilation

Hi, I am using Arria V GX FPGA and Quartus 13.1 and there are timing violations, so I need to try different PLL settings to try to fix them. Is there a way to change the PLL phase shift for examp...
Altera_Forum's avatar
Altera_Forum
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12 years ago

There is a way, but it's not very simple.

If you generate the PLL with ALTPLL_RECONFIG, instead of ALTPLL you can reprogram the PLL from within the operating system. This is usually done with a CPU either inside or outside of the block, but a few canned configurations could be setup into block rams, and initiated with a state machine if you needed to test a few configurations.

I suggest you read up on this:

http://www.altera.com/literature/ug/ug_altpll_reconfig.pdf

Regards,

Pete