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Altera_Forum
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15 years ago

Changing data width in floating point ip vs using fixed point

I am confused in trying to differentiate among the two options: Changing the default data width(32 bits) in Altera floating point ip cores vs Using fixed point ip. Are these two things not the ...
Altera_Forum's avatar
Altera_Forum
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15 years ago

I now understand the difference between fixed and floating point well. So to use the fixed point arithmetic with Verilog, is there no library support like in VHDL? Also consider the following:

reg [7:0] a;

reg [7:0] b;

reg [15:0] c;

c<=a*b;

c<=a/b;

c<=a+b;

c<=a-b;

Would the following expressions be valid for +,-,/,* operations in fixed point arithmetic? Thanks for the pointers.