carry chain tdc

Thank you for your inquiry regarding carry chain TDC implementation on Altera Agilex 9 FPGAs and achieving ~30ps resolution.

Carry Chain TDC on Agilex 9

Altera FPGAs do not provide a direct equivalent to the Xilinx CARRY4 primitive. However, carry chain logic can be inferred by implementing arithmetic structures (such as adders) in your HDL. The Quartus compiler maps these structures to the device’s carry chain resources, enabling TDC applications.

Example code and WYSIWYG usage:
You can use Altera's low-level WYSIWYG logic modules (e.g., tennm_logic_module) to directly instantiate and control carry chain resources. Example designs and code snippets are available(Check your email) for experimentation, and manual placement/routing in Quartus Chip Planner is recommended for optimal results.

Important Caveats

Based on our experience:

• Carry-based predictable delay methods are less effective on newer FPGAs (like Agilex 9) compared to older devices. Architectural changes, such as carry lookahead logic, introduce significant non-uniformity in delay steps.
• Absolute delays are decreasing in modern chips, making tap-to-tap delay smaller and harder to calibrate precisely.
• Variation in delay is increasing—bin widths are not uniform, and per-bin calibration is often necessary. Linearity and monotonicity cannot be guaranteed across the chain.
• Resolution of ~30ps is possible, but achieving consistent and predictable results is more challenging.

Recommended Alternative

For more uniform and controllable delays, we recommend experimenting with wire LUT delay lines instead of relying solely on carry chains. Wire LUTs, combined with manual placement and routing, have proven to deliver more consistent results on Agilex devices.

Measurement methodology:
Linearity is typically measured using a ring oscillator or periodic signal, sampled through your delay line. A histogram of hits per bin allows you to calculate propagation delay differences and calibrate accordingly.