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Altera_Forum
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8 years ago

carry chain delay difference between real test and Timequest analysis result

Hi all, 5CGXFC7D6F31C7N is used to implement a TDC in my design with QII14.0. according to timequest analysis results, the average carry delays of adder in a ALM are 52ps, 46ps, 27ps, 26ps respe...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

The timing model needs to account for worst case variation from the fab in each corner + design margin, have you tried sweeping the entire FPGA to see how much variation you get? It's possible you have a faster part or used a faster region on the FPGA.

Also, did you take into account clock skew in your measurement?