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Altera_Forum
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8 years ago

carry chain delay difference between real test and Timequest analysis result

Hi all, 5CGXFC7D6F31C7N is used to implement a TDC in my design with QII14.0. according to timequest analysis results, the average carry delays of adder in a ALM are 52ps, 46ps, 27ps, 26ps respe...
Altera_Forum's avatar
Altera_Forum
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8 years ago

I strongly suspect your measurement is wrong.

The main concern in the design of TDC on fpga is that your signal input will be asynchronous and can't be sampled on registers without timing violation. It also can't be synchronised through two stage registers as this will defeat the purpose.

So I don't see how TDC can sort out this issue.