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Honored Contributor
Honored Contributorcarry chain delay difference between real test and Timequest analysis result
Hi all, 5CGXFC7D6F31C7N is used to implement a TDC in my design with QII14.0. according to timequest analysis results, the average carry delays of adder in a ALM are 52ps, 46ps, 27ps, 26ps respe...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- How are you measuring this delay on an internal FPGA path? --- Quote End --- Well, i chained 420 ALMs vertically, a carry signal is generated by an input (active high). then the carry signal is propagated along the (adder) chain. A 250MHz system clock is used to sample the carry signal position, then i could get to know how many ALMs the carry signal is passed within a 250MHz period(positions at two adjacent clock edges can be obtained and then subtracted). according to test result, the carry signal propagates about 360 ALMs in a 250MHz period, so i get average carry delay per ALM is 4000ps/360=11ps. you could look at the basic idea of FPGA based TDC implementation to get a deep understanding. Best Regards, ingdxdy
