Honored ContributorHi guys,
I want to make some small modification on PLL of Cyclone V devices. However, it seems i can't do anything thru ECO on it as altera previous generation deivces (for example Cyclone III). Why?
Honored ContributorThe PLLs on the Cyclone V don't work the same as the earlier parts. Read the PLL chapter of the device handbook. Since you didn't give any details on what you were trying, I can't say why it doesn't work.
Honored ContributorHonored ContributorHello, have you tried to follow http://electro-logic.blogspot.it/2015/09/fpga-engineering-change-orders.html (hello, have you tried to follow http://electro-logic.blogspot.it/2015/09/fpga-engineering-change-orders.html) ?
I think it is done with Cyclone IV but should works also with Cyclone V. Are you using Cyclone V PLL IP? Tutorial is in Italian but you can translate it with Google or Bing.Honored ContributorAltera app note 661 "Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores" seems to explain how to do this. Examples 2 and 4 are on phase shift. This is different from Cyclone IV.
Honored ContributorHonored ContributorYeah, with Cyclone V you have to use Altera PLL Reconfig IP
Honored ContributorHonored ContributorAs far as I can tell, flz47655 is correct. The only way to changes the phase of a clock after compilation on Cyclone V is to implement PLL reconfiguration with the Altera IP.
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