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Altera_Forum
Honored Contributor
10 years agoAs far as I can tell, flz47655 is correct. The only way to changes the phase of a clock after compilation on Cyclone V is to implement PLL reconfiguration with the Altera IP.
As far as I can tell, flz47655 is correct. The only way to changes the phase of a clock after compilation on Cyclone V is to implement PLL reconfiguration with the Altera IP.