can't boot from sram

you have two images to flash on the EPCS. First the .sof file that contains the hardware, and then the .elf file that contains the software.

The bootloader included in the EPCS controller will read from the EPCS flash, jump over the hardware image and copy the .elf file contents to the SRAM.

To flash the .elf file in the EPCS you can use the nios programmer.

Hi

I am having similar problems. I have run out of on chip memory space on my cyclone I device and so I need to be able to boot my software from my volatile SRAM after power cycle.

I'm not clear on exactly what i need to do to do this. So far i have been setting the reset vector to the EPCS and exceptions to on-chip RAM in sopc builder and in NIOS IDE my BSP linker list i have changed all the linker sections (except the grayed .entry and .exceptions) to my SRAM.

If i upload my newly compiled .sof in quartus via jtag everything works? but if i upload to EPCS to run without jtag it only appears to retain the hardware design and not the software?? I need them both to be there on power cycle.

Does anyone have experience of making this work and is it possible to do this?

Jockeyjim

Hi Sailor!

Are you programming your EPCS with the software (and hardware, for that matter) after setting the reset vector there? That's what must be done with EPCS or CFI (serial and parallel) flash devices.

After that everything should work.

Cheers,

--slacker

hi, Satish. The program can run without sram or sram just used for storing data.

When I want boot copier to load boot section onto sram, it does't work.

I do an experiment that sopc just with on chip memory and EPCS, pio, cpu. I set reset vector and exception vector to on chip memory, it works. but I set these vector to EPCS, it does't work when power on. just work after debug with JTAG.

Did any one have experience that boot with sram? When program bigger and bigger, the .text section can't be set to on chip memory, I found some reference said that the program can boot with CFI(.text set to CFI), but CFI is not fast enough, I think there be a method let the program boot on SRAM , of course, the program stored in EPCS or CFI.

Confirm if you have done these:

- Reset vector for CPU in SOPC builder should point to EPCS

- Add EPCS and SRAM as slaves to CPU data master and instruction master

Satish