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Altera_Forum
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16 years ago

can't boot from sram

I build sopc with epcs component, with the reset vector and exception vector at sram section, and set .text section at sram section, I have changed the sram width from 32 bit to 8 bit, but I still ca...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Hi

I am having similar problems. I have run out of on chip memory space on my cyclone I device and so I need to be able to boot my software from my volatile SRAM after power cycle.

I'm not clear on exactly what i need to do to do this. So far i have been setting the reset vector to the EPCS and exceptions to on-chip RAM in sopc builder and in NIOS IDE my BSP linker list i have changed all the linker sections (except the grayed .entry and .exceptions) to my SRAM.

If i upload my newly compiled .sof in quartus via jtag everything works? but if i upload to EPCS to run without jtag it only appears to retain the hardware design and not the software?? I need them both to be there on power cycle.

Does anyone have experience of making this work and is it possible to do this?

Jockeyjim